Data storage device and data fetching method for flash memory

ABSTRACT

A data storage device is provided. The data storage device, coupled to a host, includes: a flash memory; and a controller, configured to control accessing of the flash memory; wherein when the host performs random data accessing to the flash memory, the controller retrieves address information of a corresponding block and a corresponding page in the flash memory associated with first data to be read based on a global mapping table, and pre-fetches the corresponding page from the flash memory based on the address information; wherein when the controller obtains the address information, the controller further determines whether the first data is located in a current buffer block based on a local mapping table; wherein when the first data is located in the current buffer block, the controller further cancels the pre-fetched corresponding page, and reads the first data from the current buffer block.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Application No.61/837,515, filed Jun. 20, 2013, the entirety of which is incorporatedby reference herein

This Application claims priority of Taiwan Patent Application No.103117734, filed on May 21, 2014, the entirety of which is incorporatedby reference herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a flash memory, and in particular, to adata storage device including a flash memory and data fetching method ofa flash memory.

2. Description of the Related Art

Flash memory is a common non-volatile data storage device, which can beerased and programmed electrically. For example, a NAND flash memory isusually for use in a memory card, a USB flash device, a solid-state disk(SSD), an embedded multimedia card, etc.

The storage array in a flash memory (e.g. NAND flash) includes multipleblocks, such as spare blocks and data blocks. Each block includesmultiple pages. When some data are written into the flash memory, theintermediate data may be temporarily stored in a current buffer block ofthe spare blocks. When all pages in the current buffer block are writtenwith data, the current buffer block may become a data block. Whenperforming random accessing of the flash memory, some data may be stillstored in the current buffer block. However, a conventional flash memorycontroller usually determines whether the data to be accessed is locatedin the current buffer block or in the data blocks, resulting inperformance loss.

BRIEF SUMMARY OF THE INVENTION

A detailed description is given in the following embodiments withreference to the accompanying drawings.

In an exemplary embodiment, a data storage device is provided. The datastorage device, coupled to a host, includes: a flash memory; and acontroller, configured to control accessing of the flash memory; whereinwhen the host performs random data accessing to the flash memory, thecontroller retrieves address information for a corresponding block and acorresponding page in the flash memory associated with first data to beread based on a global mapping table, and pre-fetches the correspondingpage from the flash memory based on the address information; whereinwhen the controller obtains the address information, the controllerfurther determines whether the first data is located in a current bufferblock based on a local mapping table; wherein when the first data islocated in the current buffer block, the controller further cancels thepre-fetched corresponding page, and read the first data from the currentbuffer block.

In another exemplary embodiment, a data fetching method for a flashmemory is provided. The method is for use in a data storage devicecoupled to a host, wherein the data storage device comprises a flashmemory and a controller. The data fetching method includes the steps of:retrieving address information of a corresponding block and acorresponding page in the flash memory associated with first data to beread based on a global mapping table of the controller, and pre-fetchingthe corresponding page from the flash memory based on the addressinformation when the host performs random data accessing to the flashmemory; determining whether the first data to be read is located in acurrent buffer block based on a local mapping table of the controllerwhen the controller obtains the address information; and cancelling thepre-fetched corresponding page, and reading the first data from thecurrent buffer block when the first data is located in the currentbuffer block.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention can be more fully understood by reading thesubsequent detailed description and examples with references made to theaccompanying drawings, wherein:

FIG. 1 is a block diagram of an electronic system in accordance with anembodiment of the invention; and

FIG. 2 is a flow chart of a data fetching method for use in a flashmemory in accordance with an embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

The following description is of the best-contemplated mode of carryingout the invention. This description is made for the purpose ofillustrating the general principles of the invention and should not betaken in a limiting sense. The scope of the invention is best determinedby reference to the appended claims.

FIG. 1 is a block diagram of an electronic system in accordance with anembodiment of the invention. The electronic system 100 may comprise ahost 110 and a data storage device 120. The data storage device 120 maycomprise a flash memory 130 and a controller 140, wherein the datastorage device 120 is operated based on the instructions/commands fromthe host 110. The controller 140 may comprise a computation unit 142 anda memory unit (e.g. read-only memory, random access memory, registers)144. The program codes and data stored in the memory unit 144 may befirmware executed by the computation unit 142, so that the controller140 may control the flash memory 130 based on the firmware. The flashmemory 130 may comprise a plurality of blocks, and each block comprisesa plurality of pages.

In an embodiment, the flash memory 130 may comprise a spare block pool150, and a data block pool 160. The spare block pool 150 comprises aplurality of spare blocks 15 l˜15 n for storing invalid data. The datablock pool 160 comprise a plurality of data blocks 16 l˜16 m for storingdata. In an embodiment, the controller 140 may manage the blocks of theflash memory 130 according to the commands from the host 110. A block inthe flash memory 130 is assigned based on a physical address, and thehost 110 may assign a block based on a logical address. Accordingly, thecontroller 140 has to convert the logical address from the host 110 to aphysical address. In an embodiment, the controller 140 may record therelationship between the logical addresses and physical addresses intoan address link table. In an embodiment, the controller 140 records therelationship between the logical addresses and physical addresses intoat least one address link table such as a global mapping table 147 and alocal mapping table 148. For example, the global mapping table 147 is ahost-to-flash table, and the local mapping table 148 is a flash-to-hosttable. In an embodiment, the global mapping table 147 and the localmapping table 148 are stored in the memory unit 130.

In an embodiment, each of the data blocks 16 l˜16 m may comprise aplurality of pages. When data is stored in a page of the data blocks,the page can be regarded as a data page. When the page has acorresponding logical address, the page can be regarded as a valid page.In an embodiment, the global mapping table 147 records the physicaladdress of the data from the host 110 in the flash memory 130. The localmapping table 148 records the data pages from the host 110 in thecurrent buffer block of the flash memory 130. Generally, the number oflinks stored in the global mapping table 147 is much larger than thatstored in the local mapping table 148.

When all pages in the current buffer block are written with data fromthe host 110, the current buffer block becomes a data block, and therelationship between the logical address and physical address of thedata block is written into the global mapping table 147.

In an embodiment, when the host 110 writes data to the flash memory 130,the controller 140 may correctly write data into the current bufferblock of the flash memory based on the global mapping table 147, andupdate the status of the data pages of the current buffer block of theflash memory 130 in the local mapping table 148. Specifically, when allpages in the current buffer block are written with data from the host110, the controller 140 may set the current buffer block as a datablock, and update the link relationship of data blocks in the globalmapping table 147, and flush the local mapping table 148 storing theprevious current buffer block.

In an embodiment, the controller 140 may further comprise a searchingcircuit 146, configured to check the addresses recorded in the localmapping table 148 one by one, thereby determining whether the data to beaccessed is located in the current buffer block. When the computationunit 142 performs random data accessing, the controller 140 may read thelocal mapping table 148 to determine whether the data to be accessed islocated in the current buffer block. If so, the controller 140 mayretrieve the data from the current buffer block directly. If not, thecontroller 140 may retrieve the physical address of the data in theflash memory 130 (e.g. page B of block B) from the global mapping table147, and then read the data from the retrieved physical address of theflash memory 130. It should be noted that the controller has to delivera read command from the host 110 to the flash memory 130 before thecontroller 140 queries the physical address from the global mappingtable 147, and the controller 140 has to wait for a busy time before theflash memory 130 is ready for accessing. If the data to be read by thehost 110 cannot be obtained by querying the local mapping table 148, thecontroller 140 has to send a read command and wait for the flash memory130 to be ready for accessing.

In another embodiment, when the CPU or hardware of the host 110 is toperform random data accessing, the computation unit 142 of thecontroller 140 may directly pre-fetch data from the flash memory 130based on the link relationship of the global mapping table 147 (e.g.directly read page B of block B), and the searching unit 146 may checkthe address data of the local mapping table 148 to determine whether thedata of the host page to be read is located in the current buffer block.If so, the controller may cancel the pre-fetched data, and thecomputation unit 142 may send a read command again to retrieve thecorrect data from the current buffer block. If not, the controller 140may obtain the desired data from the pre-fetched data (e.g. page B ofblock B). In the embodiment, the operations for pre-fetching from theflash memory 130 and checking address data in the local mapping table148 can be performed almost simultaneously. Compared with the previousembodiment, in which these two operations can only be performedsequentially, the computation time can be significantly reduced whenperforming random accessing of the flash memory. It should be notedthat, the order of these two operations for pre-fetching from the flashmemory 130 and checking address data in the local mapping table 148 canbe exchanged because these two operations are performed almostsimultaneously. Accordingly, these two operations can be performed inparallel to reduce the computation time when performing random accessingto the flash memory 130.

FIG. 2 is a flow chart of a data fetching method for use in a flashmemory in accordance with an embodiment of the invention. As illustratedin FIG. 2, the computation unit 142 of the controller 140 may retrievethe address information of a corresponding block and a correspondingpage in the flash memory 130 associated with the first data (step S210),and pre-fetch the corresponding page of the first data from the flashmemory 130 based on the address information (e.g. the data is read to aread-out cache buffer of the controller 140 (not shown) (step S220).Subsequently, the searching circuit 146 of the controller 140 may checkwhether the local mapping table 148 records the address informationassociated with the first data (step S230), and determine whether thefirst data to be read is located in a current buffer block of the flashmemory 130 (step S240). If so, the computation unit 142 of thecontroller 140 may cancel the pre-fetched corresponding page (stepS250), and read the first data from the current buffer block (stepS260). If not, the computation unit 142 of the controller 140 maydirectly read the first data from the pre-fetched corresponding page(step S270).

While the invention has been described by way of example and in terms ofthe preferred embodiments, it is to be understood that the invention isnot limited to the disclosed embodiments. On the contrary, it isintended to cover various modifications and similar arrangements (aswould be apparent to those skilled in the art). Therefore, the scope ofthe appended claims should be accorded the broadest interpretation so asto encompass all such modifications and similar arrangements.

What is claimed is:
 1. A data storage device, coupled to a host, thedata storage device comprising: a flash memory; and a controller,configured to control accessing of the flash memory; wherein when thehost performs random data accessing of the flash memory, the controllerretrieves address information of a corresponding block and acorresponding page in the flash memory associated with first data to beread based on a global mapping table of the controller, and pre-fetchesthe corresponding page from the flash memory based on the addressinformation; wherein when the controller obtains the addressinformation, the controller further determines whether the first data tobe read is located in a current buffer block based on a local mappingtable of the controller; wherein when the first data is located in thecurrent buffer block, the controller further cancels the pre-fetchedcorresponding page, and reads the first data from the current bufferblock.
 2. The data storage device as claimed in claim 1, wherein theglobal mapping table records mapping relationships from a logicaladdress to a physical address between the host and the flash memory, andthe local mapping table records a status of data pages from the host inthe current buffer block.
 3. The data storage device as claimed in claim1, wherein the controller further comprises: a computation unit,configured to retrieve the address information of the first data fromthe global mapping table; and a searching circuit, configured to checkwhether the local mapping table records the address informationassociated with the first data, thereby determining whether the firstdata is located in the current buffer block.
 4. The data storage deviceas claimed in claim 1, wherein when the first data is not located in thecurrent buffer block, the controller directly obtains the first datafrom the pre-fetched corresponding page.
 5. The data storage device asclaimed in claim 1, wherein when the first data is located in thecurrent buffer block, the controller further sends a read command to theflash memory, thereby reading the first data from the current bufferblock.
 6. A data fetching method for a flash memory, for use in a datastorage device coupled to a host, wherein the data storage devicecomprises a flash memory and a controller, the data fetching methodcomprising: retrieving address information of a corresponding block anda corresponding page in the flash memory associated with first data tobe read based on a global mapping table of the controller, andpre-fetching the corresponding page from the flash memory based on theaddress information when the host performs random data accessing to theflash memory; determining whether the first data to be read is locatedin a current buffer block based on a local mapping table of thecontroller when the controller obtains the address information; andcancelling the pre-fetched corresponding page, and reading the firstdata from the current buffer block when the first data is located in thecurrent buffer block.
 7. The method as claimed in claim 6, wherein theglobal mapping table records mapping relationship from a logical addressto a physical address between the host and the flash memory, and thelocal mapping table records a status of data pages from the host in thecurrent buffer block.
 8. The method as claimed in claim 6, wherein thecontroller further comprises: a computation unit, configured to retrievethe address information of the first data from the global mapping table;and a searching circuit, configured to check whether the local mappingtable records the address information associated with the first data,thereby determining whether the first data is located in the currentbuffer block.
 9. The method as claimed in claim 6, further comprising:directly obtaining the first data from the pre-fetched correspondingpage when the first data is not located in the current buffer block. 10.The method as claimed in claim 6, further comprising: sending a readcommand to the flash memory by the controller to read the first datafrom the current buffer block when the first data is located in thecurrent buffer block.